Typically, during the manufacturing process of an IC, testing (probing) is performed on the IC prior to the time the IC is mounted into a package. In some instances the probing is performed after the IC is mounted. However, in situations where multiple ICs are stacked into tiers, it is difficult to probe the ICs due to inaccessibility of test terminals on the outside of the stacked device.
The problem is compounded when a tier does not include a complete circuit. Thus, in situations where portions of a testable circuit are constructed on different tiers, it is not feasible to test the complete circuit until the dies are stacked into the final multi-tiered IC device (also referred to as a stacked IC device). Moreover, once stacked accessibility for test purposes may be limited.
One solution to this problem is to bring test leads to accessible locations on the periphery of the stacked device. This, however, in many situations is either not possible due to space constraints, signal propagation times, or simply because it is too expensive. Another problem is that the small size of stacked devices may require small electrical pads and through silicon vias (TSV), which may range in size to less than 10 microns, which in turn do not easily lend to testing with conventional probe tips (typically 25-50 microns). For testing, multiple probe tips usually must make contact at the same time, so even when each individual probe tip is small enough, a large number of probe tips becomes difficult to manage.